Energy efficient reduce and rank using input adaptive approximations
  Sign-magnitude encoding for efficient vlsi realization of decimal multiplication
  Adaptive multibit crosstalk-aware error control coding scheme for on-chip communication
  Dual-quality 4:2 compressors for utilizing in dynamic accuracy configurable multipliers
  A way-filtering-based dynamic logical–associative cache architecture for low-energy consumption
  A high-efficiency 6.78-mhz full active rectifier with adaptive time delay control for wireless power transmission
  High-speed and low-latency ecc processor implementation over gf(2m) on fpga
  A 2.5-ps bin size and 6.7-ps resolution fpga time-to-digital converter based on delay wrapping and averaging
  Comedi: combinatorial election of diagnostic vectors from detection test sets for logic circuits
  Low-power scan-based built-in self-test based on weighted pseudorandom test pattern generation and reseeding
  A 2.4–3.6-ghz wideband sub-harmonically injection-locked pll with adaptive injection timing alignment technique
  fast automatic frequency calibrator using an adaptive frequency search algorithm A 65-nm cmos constant current source with reduced pvt variation
  High-speed parallel lfsr architectures based on improved state-space transformations
  Scalable approach for power droop reduction during scan-based logic bist
  Soft error rate reduction of combinational circuits using gate sizing in the presence of process variations
  Stochastic implementation and analysis of dynamical systems similar to the logistic map
  Roba multiplier: a rounding-based approximate multiplier for high-speed yet energy-efficient digital signal processing
  Vlsi design of 64bit × 64bit high performance multiplier with redundant binary encoding
  A method to design single error correction codes with fast decoding for a subset of critical bits
  Evaluating Secrecy Outage of Physical Layer Security in Large-Scale MIMO Wireless Communications for Cyber-Physical Systems
  Congestion Detection and Propagation in Urban Areas Using Histogram Models
  Hybrid hardware/software floating-point implementations for optimized area and throughput tradeoffs
  Efficient soft cancelation decoder architectures for polar codes
  Low-complexity digit-serial multiplier over gf(2m) based on efficient toeplitz
  block toeplitz matrix–vector product decomposition
  Coordinate rotation-based low complexity k-means clustering architecture
  Energy-efficient vlsi realization of binary64 division with redundant number systems
  Hardware-efficient built-in redundancy analysis for memory with various spares
  Reordering tests for efficient fail data collection and tester time reduction
  An fpga-based hardware accelerator for traffic sign detection
  Antiwear leveling design for ssds with hybrid ecc capability
  A fault tolerance technique for combinational circuits based on selective-transistor redundancy