VLSI

VLSI

Very large-scale integration (VLSI) is the process of integrating or embedding hundreds of thousands of transistors on a single silicon semiconductor microchip. VLSI technology was conceived in the late 1970s when advanced level computer processor microchips were under development. VLSI is a successor to large-scale integration (LSI), medium-scale integration (MSI) and small-scale integration (SSI) technologies.

VLSI PROJECTS LIST

1. Energy efficient reduce and rank using input adaptive approximations
2. Sign-magnitude encoding for efficient vlsi realization of decimal multiplication 3. Adaptive multibit crosstalk-aware error control coding scheme for on-chip communication
4. Dual-quality 4:2 compressors for utilizing in dynamic accuracy configurable multipliers
5. A way-filtering-based dynamic logical–associative cache architecture for low-energy consumption
6. A high-efficiency 6.78-mhz full active rectifier with adaptive time delay control for wireless power transmission
7. High-speed and low-latency ecc processor implementation over gf(2m) on fpga
8. A 2.5-ps bin size and 6.7-ps resolution fpga time-to-digital converter based on delay wrapping and averaging
9. Comedi: combinatorial election of diagnostic vectors from detection test sets for logic circuits
10. Low-power scan-based built-in self-test based on weighted pseudorandom test pattern generation and reseeding
11. A 2.4–3.6-ghz wideband sub-harmonically injection-locked pll with adaptive injection timing alignment technique
12. fast automatic frequency calibrator using an adaptive frequency search algorithm A 65-nm cmos constant current source with reduced pvt variation
13. High-speed parallel lfsr architectures based on improved state-space transformations
14. Scalable approach for power droop reduction during scan-based logic bist
15. Soft error rate reduction of combinational circuits using gate sizing in the presence of process variations
16. Stochastic implementation and analysis of dynamical systems similar to the logistic map
17. Roba multiplier: a rounding-based approximate multiplier for high-speed yet energy-efficient digital signal processing
18. Vlsi design of 64bit × 64bit high performance multiplier with redundant binary encoding
19. A method to design single error correction codes with fast decoding for a subset of critical bits
20. Evaluating Secrecy Outage of Physical Layer Security in Large-Scale MIMO Wireless Communications for Cyber-Physical Systems
21. Congestion Detection and Propagation in Urban Areas Using Histogram Models
22. Hybrid hardware/software floating-point implementations for optimized area and throughput tradeoffs
23. Efficient soft cancelation decoder architectures for polar codes
24. Low-complexity digit-serial multiplier over gf(2m) based on efficient toeplitz
25. block toeplitz matrix–vector product decomposition
26. Coordinate rotation-based low complexity k-means clustering architecture
27. Energy-efficient vlsi realization of binary64 division with redundant number systems
28. Hardware-efficient built-in redundancy analysis for memory with various spares
29. Reordering tests for efficient fail data collection and tester time reduction
30. An fpga-based hardware accelerator for traffic sign detection
31. Antiwear leveling design for ssds with hybrid ecc capability
32. A fault tolerance technique for combinational circuits based on selective-transistor redundancy


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1000

PROJECT DOMAINS

20000

STUDENTS SERVED

1000

PROJECT DOMAINS

5

YEARS EXPERIENCE

IEEE PROJECTDOMAINS



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