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IEEE VLSI PROJECTS: A Modified Partial Product Generator for Redundant Binary Multipliers.
An Efficient Hardware Implementation of Canny Edge Detection Algorithm.
Approximate Radix-8 Booth Multipliers for Low-Power and High-Performance Operation.
A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications.
The Serial Commutator (SC) FFT.
An Improved Signed Digit Representation Approach for Constant Vector Multiplication.
High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels.
A New XOR-Free Approach for Implementation of Convolutional Encoder.
Energy and Area Efficient Three-Input XOR/XNORs With Systematic Cell Design Methodology.
Approximate Radix-8 Booth Multipliers for Low-Power and High-Performance Operation.
Implementation of a PID control PWM Module on FPGA.
Built-in Self Testing of FPGAs.
An FPGA-Based Cloud System for Massive ECG Data Analysis.
Distributed Sensor Network-on-Chip for Performance Optimization of Soft-Error-Tolerant Multiprocessor System-on-Chip.
VLSI Implementation of Fully Parallel LTE Turbo Decoders.
A High Throughput List Decoder Architecture For Polar Codes.
High-Performance NB-LDPC Decoder With Reduction of Message Exchange.
A High-Speed FPGA Implementationof an RSD-Based ECC Processor.
Low-Power ECG-Based Processor forPredicting Ventricular Arrhythmia.
In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers.
Configurable Parallel Hardware Architecture forEfficient Integral Histogram Image Computing.
Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding.
A Normal I/O Order Radix-2 FFT Architecture to ProcessTwin Data Streams for MIMO.
Unequal-Error-Protection Error Correction Codes for theEmbedded Memories in Digital Signal Processors.
A High-Performance FIR Filter Architecture forFixed and Reconfigurable Applications.
Hybrid LUT/Multiplexer FPGA Logic Architectures.
A Dynamically Reconfigurable Multi-ASIP Architecture forMultistandard and Multimode Turbo Decoding.
Low-Power Split-Radix FFT Processors Using Radix-2 Butterfly Units.
A Fully Digital Front-End Architecture for ECGAcquisition System With 0.5 V Supply.
A Low-cost and Modular Receiver for MIMO SDR.
High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator.
Frequency-Boost Jitter Reduction forVoltage-Controlled Ring Oscillators.
Low-Energy Power-ON-Reset Circuit for Dual Supply SRAM.
Low-Power Variation-Tolerant Nonvolatile Lookup Table Design.
A Low-Power Robust Easily CascadedPentaMTJ-Based Combinational and Sequential Circuits.
A 0.1–3.5-GHz Duty-Cycle Measurement andCorrection Technique in 130-nm CMOS.
Full-Swing Local Bitline SRAM ArchitectureBased on the 22-nm FinFET Technology for Low-Voltage Operation.
A Robust Energy/Area-Efficient Forwarded-ClockReceiver With All-Digital Clock and Data Recovery in 28-nm CMOS for High-Density Interconnects.
OTA-Based Logarithmic Circuit for ArbitraryInput Signal and Its Application.
A Single-Ended With Dynamic Feedback Control8T Subthreshold SRAM Cell.
Graph-Based Transistor Network GenerationMethod for Supergate Design.
Implementing Minimum-Energy-Point SystemsWith Adaptive Logic.
A 0.52/1 V Fast Lock-in ADPLL for Supporting DynamicVoltage and Frequency Scaling.

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600026
+91 44 4203 2818
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