IEEE VLSI Projects
IEEE VLSI Projects 2016-2017

1.A Modified Partial Product Generator for Redundant Binary Multipliers

2.An Efficient Hardware Implementation of Canny Edge Detection Algorithm

3.Approximate Radix-8 Booth Multipliers for Low-Power and High-Performance Operation

4.A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications

5.The Serial Commutator (SC) FFT

6.An Improved Signed Digit Representation Approach for Constant Vector Multiplication

7.High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels

8.A New XOR-Free Approach for Implementation of Convolutional Encoder

9.Energy and Area Efficient Three-Input XOR/XNORs With Systematic Cell Design Methodology

10.Approximate Radix-8 Booth Multipliers for Low-Power and High-Performance Operation

11.Implementation of a PID control PWM Module on FPGA

12.Built-in Self Testing of FPGAs

13.An FPGA-Based Cloud System for Massive ECG Data Analysis

14.Distributed Sensor Network-on-Chip for Performance Optimization of Soft-Error-Tolerant Multiprocessor System-on-Chip

15.VLSI Implementation of Fully Parallel LTE Turbo Decoders

16.A High Throughput List Decoder Architecture For Polar Codes

17.High-Performance NB-LDPC Decoder With Reduction of Message Exchange

18.A High-Speed FPGA Implementationof an RSD-Based ECC Processor

19.Low-Power ECG-Based Processor forPredicting Ventricular Arrhythmia

20.In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers

21.Configurable Parallel Hardware Architecture forEfficient Integral Histogram Image Computing

22.Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding

23.A Normal I/O Order Radix-2 FFT Architecture to ProcessTwin Data Streams for MIMO

24.Unequal-Error-Protection Error Correction Codes for theEmbedded Memories in Digital Signal Processors

25.A High-Performance FIR Filter Architecture forFixed and Reconfigurable Applications

26.Hybrid LUT/Multiplexer FPGA Logic Architectures

27.A Dynamically Reconfigurable Multi-ASIP Architecture forMultistandard and Multimode Turbo Decoding

28.Low-Power Split-Radix FFT Processors Using Radix-2 Butterfly Units

29.A Fully Digital Front-End Architecture for ECGAcquisition System With 0.5 V Supply

30.A Low-cost and Modular Receiver for MIMO SDR

31.High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator

32.Frequency-Boost Jitter Reduction forVoltage-Controlled Ring Oscillators

33.Low-Energy Power-ON-Reset Circuit for Dual Supply SRAM

34.Low-Power Variation-Tolerant Nonvolatile Lookup Table Design

35.A Low-Power Robust Easily CascadedPentaMTJ-Based Combinational and Sequential Circuits

36.A 0.1–3.5-GHz Duty-Cycle Measurement andCorrection Technique in 130-nm CMOS

37.Full-Swing Local Bitline SRAM ArchitectureBased on the 22-nm FinFET Technology for Low-Voltage Operation

38.A Robust Energy/Area-Efficient Forwarded-ClockReceiver With All-Digital Clock and Data Recovery in 28-nm CMOS for High-Density Interconnects

39.OTA-Based Logarithmic Circuit for ArbitraryInput Signal and Its Application

40.A Single-Ended With Dynamic Feedback Control8T Subthreshold SRAM Cell

41.Graph-Based Transistor Network GenerationMethod for Supergate Design

42.Implementing Minimum-Energy-Point SystemsWith Adaptive Logic

43.A 0.52/1 V Fast Lock-in ADPLL for Supporting DynamicVoltage and Frequency Scaling

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